A 2000 frames / s programmable binary image processor chip for real time machine vision applications

Industrial manufacturing today requires both an efficient production process and an appropriate quality standard of each produced unit. The number of industrial vision applications, where real time vision systems are utilized, is continuously rising due to the increasing automation. Assembly lines, where component parts are manipulated by robot grippers, require a fast and fault tolerant visual detection of objects. Standard computation hardware like PC-based platforms with frame grabber boards are often not appropriate for such hard real time vision tasks in embedded systems. This is because they meet their limits at frame rates of a few hundreds images per second and show comparatively long latency times of a few milliseconds. This is the result of the largely serial working and time consuming processing chain of these systems. In contrast to that we designed an application-specific instruction processor chip which exploits massive parallelization of often used image preprocessing algorithms to minimize computation times. To get a feasible image resolution of 320 x 240 pixels at processing frame rates up to 2000 frames per second we realized an image processor on a semi-custom 0.18 μm pure logic CMOS platform. The paper presents the architecture, the performance parameters of the designed processor chip and some simulation test results. 1 Motivation and introduction The motivation to present that paper emerges from a firm tendency to substitute PC-based standard machine vision systems with smaller and faster embedded components (e. g. smart cameras), what is currently a world-wide on-going ambitious research topic [1],[2],[3]. One way to manage that is to use application specific integrated circuits (ASICs) as basic platform. The advantages of ASIC based components confront with their main weakness: the inflexible and fixed instruction set. To meet that we present a so called ASIP (application specific instruction set processor) which combines the flexibility of a GPP (General Purpose Processor) with the speed of an ASIC.